Verilog-A & Verilog-AMS Compact Modeling (.va, .vams)

@modelscript/verilog-a (languages/verilog-a) provides compiler, analog behavioral simulation, continuous DAE lowering, and SPICE netlist export for the IEEE 1857 Verilog-A and Verilog-AMS analog compact modeling language.

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Supported Extensions & Standards

Extension	Standard / Format	Description
.va	IEEE 1857 / OVI Verilog-A	Continuous-time analog behavioral hardware description language
.vams	Accellera Verilog-AMS	Mixed-signal analog/digital compact device modeling

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Key Capabilities

1. Analog Behavioral Disciplines & Natures

• Native support for physical disciplines and cross-domain nature definitions:
  • Electrical: Potential Voltage ($V$), Flow Current ($I$).
  • Thermal: Potential Temperature ($T$), Flow Power ($P$).
  • Rotational / Mechanical: Potential Angle ($\theta$), Flow Torque ($\tau$).
• Supports branch formulation, reference nodes (ground), and conservative multi-port Kirchhoff networks.

2. Analog Contribution Statements & Dynamic Operators

• Full evaluation of continuous-time analog contribution operators (<+):$$I(p,n)<+I_{\text{sat}}(\exp \left(\frac{V(p,n)}{n{V}_t}\right)-1)+\frac{d}{dt}(C_{j}V(p,n))$$
• Dynamic Operators: Time derivative ddt(x), time integration idt(x), transport delay absdelay(x, td), and transition filters.
• Transistor Compact Models: Enables high-speed simulation of BSIM, EKV, diode, and custom micro-electro-mechanical (MEMS) behavioral models.

3. Direct DAE Lowering

• Lowers continuous behavioral equations, branch relations, and small-signal Jacobians directly into @modelscript/runtime's DAEBuilder linear memory arena.
• Eliminates intermediate C-code generation or proprietary simulator compiling steps.

4. Polyglot Projections

• Modelica (verilogAToModelica): Translates Verilog-A modules into acausal Modelica.Electrical.Analog component classes.
• SPICE (verilogAToSpice): Generates equivalent SPICE subcircuit netlists (.subckt) with nonlinear behavioral voltage/current sources (B-sources).

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Static Analysis & Device Modeling Linter Rules

The Verilog-A linter detects compact modeling bugs and numerical convergence pitfalls:

10 rules6 error4 warning Run with msx verilog-a lint

Code	Rule	Severity	Message
M7601	unassigned-analog-branch	error	Electrical port pair '<p>' and '<n>' has no constitutive branch equation in analog block.
M7602	discontinuous-derivative-expression	warning	Discontinuous time-derivative operator '<func>()' used inside conditional branch statement.
M7603	invalid-parameter-range	error	Parameter '<name>' default value <val> violates declared range '<range>'.
M7604	unbounded-exponential-growth	warning	Unbounded exponential function 'exp()' used instead of safe 'limexp()' in '<ctx>'.
M7605	port-discipline-mismatch	error	Port '<port>' has no declared discipline or mismatch with module domain.
M7606	undefined-node-reference	error	Branch access '<branch>' references undeclared node '<node>'.
M7607	duplicate-module-declaration	error	Duplicate module declaration for '<name>'.
M7608	zero-resistance-branch	error	Potential contribution '<branch>' forms an unconstrained ideal short-circuit.
M7609	floating-internal-node	warning	Internal node '<node>' is declared but never referenced in any analog branch equation.
M7610	unsupported-analog-primitive	warning	Unsupported or deprecated analog primitive '<primitive>'.

Generated from languages/verilog-a/src/lints/rules.ts. All languages →

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CLI Usage

# Lint a Verilog-A semiconductor device model
msx verilog-a lint MOS_Transistor.va

# Lower analog behavioral equations to ModelScript linear DAE arena
msx verilog-a to-dae MOS_Transistor.va --out=transistor.dae.json

# Project into standard Modelica 3.x acausal analog component
msx verilog-a to-modelica MOS_Transistor.va -o MOS_Transistor.mo

# Export to SPICE subcircuit with nonlinear behavioral sources
msx verilog-a to-spice MOS_Transistor.va -o MOS_Transistor.sub