AUTOSAR Classic & Adaptive Architecture
ModelScript delivers native, high-performance compiler support for AUTOSAR (.arxml), the international standard for automotive electronic control unit (ECU) software architectures. Engineers can parse, validate, simulate event-triggered and periodic runnables, and bridge automotive software components (SWCs) directly into continuous plant models and SysML v2 systems requirements.
Capabilities & Supported Formats
| Format | Extension | Description |
|---|---|---|
| AUTOSAR ARXML Document | .arxml, .xml | XML schema defining packages, software component types (ApplicationSwComponentType, SensorActuatorSwComponentType), internal behaviors, runnables, timing events, interfaces, and ECU network topologies. |
Key Architectural Pillars
- High-Throughput ARXML Ingestion:
- Robust XML extraction parsing software component definitions, client-server and sender-receiver interfaces, port prototypes, variable access definitions, runnable entities, and timing events via
parseArxml().
- Robust XML extraction parsing software component definitions, client-server and sender-receiver interfaces, port prototypes, variable access definitions, runnable entities, and timing events via
- In-Memory Virtual RTE Simulation Engine:
- Implements an event-driven and periodic discrete scheduler (
VirtualRte) reproducing AUTOSAR RTE semantics (Rte_Read,Rte_Write). - Routes signals across hierarchical assembly connectors (
AssemblySwConnector) between provider P-ports and requester R-ports.
- Implements an event-driven and periodic discrete scheduler (
- Automotive Static Linters (
M7401–M7408):- Detects unconnected required ports, interface signature mismatches, Worst-Case Execution Time (WCET) budget overruns against event periods, overlapping signal allocations in CAN/LIN PDUs, and cyclic runnable dependencies.
- Dual Architectural Projections:
- Modelica Standard Blocks: Translates SWCs into acausal discrete blocks for Hardware-in-the-Loop (HIL) and Software-in-the-Loop (SIL) co-simulation with 1D vehicle plant dynamics.
- SysML v2 Systems Architecture: Generates formal OMG SysML v2
part defhierarchies, connection usages, and port definitions for digital thread traceability.
- Continuous/Discrete DAE Lowering:
- Compiles SWC states, calibrated calibration parameters, and discrete runnable step functions into the
DAEBuilderSoA linear memory arena.
- Compiles SWC states, calibrated calibration parameters, and discrete runnable step functions into the
Command Line Interface (msx autosar)
ModelScript CLI provides turnkey subcommands for automotive ECU engineering:
msx autosar <action> [files...] [options]| Action | Description | Key Options |
|---|---|---|
inspect | Dumps package hierarchy, SWC components, runnable entities, timing events, and network PDUs. | — |
lint | Runs pre-flight automotive semantic checks, interface compatibility, and scheduling analysis. | — |
to-modelica | Generates Modelica standard blocks representing SWC interfaces and communication buses. | --out=<file.mo> |
to-sysml | Projects AUTOSAR composition architecture to formal OMG SysML v2 code. | --out=<file.sysml> |
to-dae | Lowers software architecture into ModelScript linear-memory DAE arena and prints statistics. | — |
simulate-rte | Executes the Virtual RTE discrete event scheduler over a configured time window. | --duration=<sec>, --step=<sec>, --out=<file.json> |
Examples
# Inspect automotive software components and timing events
msx autosar inspect PowertrainArchitecture.arxml
# Lint for unconnected R-ports, timing budget overflows, or PDU collisions
msx autosar lint BrakeController.arxml
# Project software component architecture to SysML v2 part definitions
msx autosar to-sysml SteeringSystem.arxml --out=SteeringArchitecture.sysml
# Simulate periodic runnable execution and signal routing through Virtual RTE
msx autosar simulate-rte PowertrainSystem.arxml --duration=0.5 --step=0.01 --out=rte_log.jsonAutomotive Pre-Flight Linters & Diagnostic Rules
15 rules11 error3 warning1 info Run with msx autosar lint
| Code | Rule | Severity | Message |
|---|---|---|---|
M7401 | unconnected-mandatory-port | error | Required port '<portName>' on component '<compName>' (<typeName>) is unconnected in composition '<compSwc>'. |
M7402 | interface-mismatch | error | Interface mismatch in connector '<connName>': Provider port '<pPort>' provides '<pIf>' while requester port '<rPort>' requires '<rIf>'. |
M7403 | data-element-type-mismatch | warning | Data element '<deName>' in interface '<ifName>' has no data type reference. |
M7403 | invalid-runnable-period | error | Timing event for runnable '<symbol>' defines non-positive period (<period> s). |
M7404 | duplicate-short-name | error | Duplicate SHORT-NAME '<name>' detected in package '<pkg>'. |
M7405 | invalid-data-type-mapping | error | Invalid data type mapping for '<dtName>': <reason>. |
M7405 | wcet-budget-overflow | error | Execution time WCET (<wcetMs> ms) of runnable '<runnableName>' exceeds its timing event period (<periodMs> ms). |
M7406 | circular-composition-dependency | error | Circular software component composition dependency detected: <path>. |
M7406 | overlapping-pdu-bits | error | Signals '<sigA>' and '<sigB>' overlap bit index <bitIdx> in PDU '<pduName>'. |
M7407 | missing-software-address-method | warning | Variable data prototype '<variable>' lacks a declared SwAddrMethod memory section mapping. |
M7407 | pdu-exceeds-frame-capacity | error | PDU '<pduName>' length (<pduLen> bytes) exceeds CAN frame '<frameName>' payload capacity (<frameLen> bytes). |
M7408 | cyclic-runnable-dependency | error | Cyclic data dependency detected between runnables: '<value>'. |
M7408 | incompatible-port-interface-direction | error | Port '<portName>' interface direction violation: <reason>. |
M7409 | missing-internal-behavior | warning | Atomic software component '<swcName>' lacks internal behavior definition. |
M7410 | untriggered-runnable | info | Runnable entity '<rName>' in SWC '<swcName>' has no associated RTE trigger event. |
Generated from languages/autosar/src/errors.ts. All languages →
Language Server Protocol & Registry Integration
AUTOSAR .arxml documents enjoy full language intelligence through @modelscript/lsp:
import { parseArxml, lintAutosarModel, VirtualRte, autosarToModelica, autosarToSysml } from "@modelscript/autosar";
// Parse ARXML text
const model = parseArxml(arxmlText);
// Pre-flight static checking
const diagnostics = lintAutosarModel(model);
// Virtual RTE Execution
const rte = new VirtualRte(model);
rte.registerRunnable("PedalSensor", "RE_ReadPedal", (ctx) => {
ctx.write("PedalOut", "Pos", 0.75);
});
rte.registerRunnable("EngineECU", "RE_ComputeThrottle", (ctx) => {
const pedal = Number(ctx.read("PedalIn", "Pos"));
ctx.write("ThrottleOut", "Cmd", pedal * 0.9);
});
// Advance 50 ms in 10 ms steps
const executionLog = rte.runUntil(0.05, 0.01);
