Fragmented EDA flows
Circuit, device, and channel models each need a different simulator.
Skip to contentThe challenge 01 02 03 Reference workflow Capabilities
Electronics & Semiconductors
Analog, RF, and signal integrity in one open toolchain
Simulate SPICE netlists, compile Verilog-A compact models, and integrate IBIS buffers and Touchstone S-parameters with vector fitting and passivity enforcement.
$ msx spice simulate LowPassFilter.cir --analysis op
$ msx spice simulate PowerSupply.cir --analysis tran --tstep 1e-6 --tstop 0.02 --out transient.csv
$ msx spice simulate AudioAmplifier.sp --analysis ac --format csv --out bode.csv
What slows electronics & semiconductors teams down
Non-passive macromodels
Measured S-parameters produce unstable time-domain simulations if they aren't passive.
System context missing
Electronics are rarely simulated together with the mechanical and thermal system around them.
One pipeline, end to end
- 1
Netlist
SPICE + Verilog-A devices
- 2
Channel
Touchstone & IBIS models
- 3
Simulate
OP, transient & AC
- 4
Integrate
Modelica / FMU export
What ModelScript does for you
Circuit analysis
SPICE operating point, transient, and AC analyses from the CLI.
Compact models
Compile Verilog-A behavioral models to DAEs and export SPICE netlists.
Rational macromodels
Vector fitting with Hamiltonian passivity enforcement for Touchstone data.
System-level projection
Project circuits into Modelica for multi-domain studies.
Open-core toolchain that runs anywhere
Browser, CLI, VS Code, CI pipelines, or air-gapped Enterprise Appliances (AGPL-3.0 Core & Commercial Editions).